lnd - sp64hv 32mhz, 64 channel serial to parallel converter with push - pull outputs features ? hvcmos ? technology ? 5.0v cmos logic ? output voltage up to +90v ? low power level shifting ? 32mhz equivalent data rate ? latched data outputs ? forward and reverse shifting options (dir pin) ? diode to v pp allows efficient power recovery ? outputs may be hot switched ? hi - rel processing available general description the lnd - sp64hv is a low voltage serial to high voltage parallel converter with push - pull outputs. the device has been designed for use as a driver for el displays. it can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix lcd displays. the device has 4 parallel 16 - bi t registers, permitting data rates 4x the speed of one (they are clocked together). there are also 64 latches and control logic to perform the polarity select and blanking of the outputs. hv out 1 is connected to the first stage of the first shift register t hrough the polarity and blanking logic. data is shifted through the shift registers on the logic low to high transition of the clock. the dir pin causes ccw shifting when connected to gnd, and cw shifting when connected to v dd . a data output buffer is prov ided for cascading devices. this output reflects the current status of the last bit of the shift register (hv out 64). operation of the shift register is not affected by the (latch enable), (blanking), or the (polarity) inputs. transfer of data fro m the shift registers to the latches occurs when the input is high. the data in the latches is stored when the is low. functional block diagram data sheet d ? linear dimensions, inc. ? 445 east ohio street, chicago il 60611 usa ? tel 312. 404 . 9283 ? fax 312.321.1830 ? www.lineardimensions.com ?
ordering information pin configuration device package options 80 - lead pqfp 20.00 x 14.00 mm body 3.40 mm height (max) 0.80 mm pitch lnd - sp64hv lnd - sp64hv - pg - g - g indicates package is rohs compliant (green) absolute maximum ratings parameter value supply voltage, v dd - 0.5v to +5 .5 v output voltage, v pp - 0.5v to +90v logic input levels - 0.3v to v dd +0.3v ground current 1 1.5a continuous total power dissipation 2 1200mw operating temperature range - 40 c to +85 c storage temperature range - 65 c to 150 c lead temperature 3 260 c absolute maximum ratings are those values beyond which damage t o the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages a re referenced to device ground. . notes: 1 . limited by the total power dissipated in the package 2 . for operation above 25 c ambient derate linearly to maximum operating temperature at 20mw/ c. 3 . 1.6mm(1/16inch) from case for 10 seconds recommended operating conditions sym parameter min max units v dd logic supply voltage 4.5 5.5 v v pp output voltage 8.0 9 0 v v ih high - level input voltage v dd - 0.5v v v il low - level input voltage 0 0.5 v f clk clock frequency per register 8.0 mhz t a operating free - air temperature - 40 +85 c notes: power - up sequence should be the following: 1 . apply ground. 2 . apply v dd . 3 . set all inputs (d in , clk, enable, etc.) to a known state. 4 . apply v pp . 5 . the v pp should not drop below v dd or float during operation. power - down sequence should be the reverse of the above lnd - sp64hv ? linear dimensions, inc. ? 445 east ohio street, chicago il 60611 usa ? tel 312.404.9283 ? fax 312.321.1830 ? www.lineardimensions.com ? 80 - lead pqfp (pg) (top view)
d c electrical characteristics sym parameter min max units conditions i dd v dd supply current 15 ma i pp high voltage supply current 100 a outputs high 100 a outputs low i ddq quiescent v dd supply current 100 a all v oh high level output hv out 7 5 v data out v dd 0.5 v v ol low level output hv out 7.0 v data out 0.5 v i ih high - level logic input current 1.0 a i il low - level logic input current - 1.0 a v oc high voltage clamp diode 1.0 v ac electrical characteristics ( t a = 8 5 ? c max , logic signals and data inputs have t r , t f 5ns[10% and 90% points] ) . symbol parameter min max units conditions f clk clock frequency 8.0 mhz per register t wl , t wh clock width high or low 62 ns --- t su data set - up time before clock rises 10 ns --- t h data hold time after clock rises 15 ns --- t on , t off time from latch enable to hv out 200 ns t dhl delay time clock to data high to low 70 ns t dlh delay time clock to data low to high 70 ns t dle * delay time clock to low to high 25 ns --- t wle pulse width output turn - off delay 25 ns --- t sle set - up time before clock rises 0 ns --- * t dle is not required but is recommended to produce stable hv outputs and thus minimize power dissipation and current spikes (allows internal sr output to stabilize) input and output equivalent circuits ? linear dimensions, inc. ? 445 east ohio street, chicago il 60611 usa ? tel 312.404.9283 ? fax 312.321.1830 ? www.lineardimensions.com ? lnd - sp64hv v d d i n p u t g n d l o g i c i n p u t s v d d g n d l o g i c d a t a o u t p u t d a t a o u t v d d g n d h i g h v o l t a g e o u t p u t s h v o u t
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